Computer systems and integrated circuits utilize a system clock signal to control the timing of events. One problem associated with distributing the clock signal is clock skew. Clock skew is the difference in arrival times of clock edges to different parts of a chip. Most conventional digital logic requires precise clocking, and ideal synchronous logic relies on clock signals arriving simultaneously to all. As the computer and integrated circuit industries continue to develop faster and more complex devices, less clock skew can be tolerated.
Clock skew is caused by a number of factors, including the physical length of a path for the clock signal. A typical path will include interconnections between circuit boards, fanout gates, circuit board foil paths, and integrated circuit interconnect metal. In general, a signal will take longer to travel a long path than a short one. Additionally, clock skew is caused by variation in routing impedance of the clock signal distribution in a device.
In computer systems, a clock signal is commonly distributed from a single source to multiple destinations. More complex devices typically have a greater number of destinations and require high performance data processing that operate at high clock frequencies. Clock skew reduces the maximum operating frequency of the circuit because the circuit has to be designed to take into account a worst case clock skew in order to operate reliably. For example, for a 1 GHz clock frequency, or 1 nanosecond cycle time, the tolerable clock skew is typically less than or equal to 100 picoseconds. In the event that clock skew is greater than 100 picoseconds, the sampling window of a register may acquire incorrect data.
Several techniques have been developed to reduce clock skew. System designers have attempted to reduce the variation in the physical length of an electrical path traveled by the clock signal. However, since each path may have a different impedance due to semiconductor manufacturing process variation, for example, the designer has difficulty matching path lengths.
U.S. Pat. No. 5,889,903 (“the '903 patent”), incorporated herein by reference, describes a method and apparatus for distributing an optical clock in an integrated circuit that eliminates clock skew by transmitting an infrared clocking pulse directed at the back surface of a Control Collapse Chip Connection (C4), flip chip, packaged chip. Silicon is partially transparent to infrared, so the optical clocking pulse penetrates through the silicon and is focused into P-N junction diode receivers at the front surface of the integrated circuit. The P-N junction diodes provide the electrical signals for local clocking. The optical clocking pulse is split and focused into an number of similarly configured P-N junctions distributed throughout the chip to provide local clocking so that clock skew is extremely small.
Unfortunately, as the '903 patent points out, only 1–2% of the photons are transmitted through a substrate that is approximately 720 um thick. The '903 patent addresses this problem in one embodiment by locally thinning the bulk silicon extending over the P-N junction receivers. However, this requires aligning, patterning, and other processing steps for both front and back surfaces of the wafer, adding substantially to cost.
Another problem with directing light through the substrate, as described by the '903 patent, is that the electrical conversion of the clocking signal may be blurred if the light passes through a substantial thickness of substrate. Light absorbed in the substrate generates minority carriers that have long lifetimes, for example, in the hundreds of microseconds in single crystal silicon. The minority carriers persist for orders of magnitude longer than the clocking signal. The P-N junctions gradually collect these minority carriers, providing a background noise signal that decreases the signal to noise ratio of the clocking signal. This is particularly a problem if only 1–2% of the optical signal penetrates through the substrate to thin heavily doped regions.
There is also a problem because the minority carrier lifetime is shorter on the heavily doped side of the junction, so that light absorbed there is not as likely to generate minority carriers that diffuse to the junction and contribute to current output of the device. Thus, the noise is high and the signal is low.
However, the technique described by the '903 patent is uniquely suited to C4 packaging technology where the back side of the integrated circuit is exposed. Conventional integrated circuits may have a number of metal interconnect layers on the front surface of a chip that would block optical signals coming from the front. The '903 patent uses front side C4s for connections and avoids shadowing clocking signal reception by directing the clocking signal to the back side of the integrated circuit and through the chip to receivers on the front side.
What is therefore needed is an improvement that more effectively provides synchronized optical clocking signals to a plurality of circuit components on a silicon substrate with minimal signal degradation and a better signal to noise ratio while continuing to avoid shadowing from metal interconnect layers on the front surface of the chip so as to minimize or eliminate clock skew.